1. Field of the Invention
The invention relates to a data latch, and more particularly, to a high-speed data latch.
2. Description of the Prior Art
A data latch is a common device used in digital circuits for latching an input signal. For instance, a conventional flip-flop composed of two latches is often used for implementing a frequency divider in a digital circuit. However, as a result of the ever-increasing operating speeds of digital circuits, one important issue is to overcome the slow response speed of the latch. Please refer to FIG. 1 showing a schematic diagram of high-speed latch 10 implemented using NMOS transistors according to the prior art. As shown in FIG. 1, the high-speed latch 10 includes a clocked current source 20, a differential amplifier 30, and a latch unit 40. The clocked current source 20 includes three NMOS transistors 22, 24, 26. The NMOS transistors 22 and 24 are enabled (turned on) by the clock signals CKP and CKN, respectively. Please note that the clock signal CKN is an inverse signal of the clock signal CKP. Therefore, the NMOS transistors 22, 24 are alternately enabled. As shown in FIG. 1, the NMOS transistor 26 is enabled by a predetermined bias voltage Vbias to provide the enabled NMOS transistor 22 or 24 with a predetermined current Ibias.
The differential amplifier 30 has two NMOS transistors 32, 34 and two resistors 36, 38, wherein nodes A, B correspond to the output terminals of the differential amplifier 30. Because the differential amplifier 30 is well-understood to those of ordinary skill in the art, further description of the differential amplifier 30 is omitted for the sake of brevity. The latch unit 40 has a cross-coupling pair established by the NMOS transistors 42, 44. Consequently, when the clock signal CKP is logic high, the differential amplifier 30 is enabled to allow the differential input signals Vin+, Vin− to drive the differential output signals Vout+, Vout− outputted from nodes A and B, respectively. Then, the differential amplifier 30 is disabled due to the clock signal CKP being logic low. The latch unit 40 then holds the output signals Vout+, Vout− until the clock signal CKP becomes logic high again.
Please note that the resistors 36 and 38 are needed to act as a load of the differential amplifier 30. Due to the semiconductor process, the resistors 36 and 38 require a large area of space within the integrated circuit. Therefore, if the conventional latch 10 shown in FIG. 1 is utilized in the digital circuit, the required chip area of the corresponding integrated circuit is large owing to the large-size resistors 36 and 38.